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Fix ~3500 analyser issues

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See merge request ryubing/ryujinx!44
This commit is contained in:
MrKev
2025-05-30 17:08:34 -05:00
committed by LotP
parent 417df486b1
commit 361d0c5632
622 changed files with 3080 additions and 2652 deletions
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2
src/ARMeilleure/CodeGen/Arm64/Arm64Optimizer.cs
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@@ -254,7 +254,7 @@ namespace ARMeilleure.CodeGen.Arm64
private static bool IsMemoryLoadOrStore(Instruction inst)
{
return inst == Instruction.Load || inst == Instruction.Store;
return inst is Instruction.Load or Instruction.Store;
}
private static bool ConstTooLong(Operand constOp, OperandType accessType)

1
src/ARMeilleure/CodeGen/Arm64/Assembler.cs
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@@ -774,6 +774,7 @@ namespace ARMeilleure.CodeGen.Arm64
instI |= 1 << 22; // sh flag
imm >>= 12;
}
WriteInstructionAuto(instI | (EncodeUImm12(imm, 0) << 10), rd, rn);
}
else

2
src/ARMeilleure/CodeGen/Arm64/CodeGenCommon.cs
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@@ -52,7 +52,7 @@ namespace ARMeilleure.CodeGen.Arm64
// Any value AND all ones will be equal itself, so it's effectively a no-op.
// Any value OR all ones will be equal all ones, so one can just use MOV.
// Any value XOR all ones will be equal its inverse, so one can just use MVN.
if (value == 0 || value == ulong.MaxValue)
if (value is 0 or ulong.MaxValue)
{
immN = 0;
immS = 0;

3
src/ARMeilleure/CodeGen/Arm64/CodeGenContext.cs
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@@ -1,6 +1,7 @@
using ARMeilleure.CodeGen.Linking;
using ARMeilleure.CodeGen.RegisterAllocators;
using ARMeilleure.IntermediateRepresentation;
using Microsoft.IO;
using Ryujinx.Common.Memory;
using System;
using System.Collections.Generic;
@@ -14,7 +15,7 @@ namespace ARMeilleure.CodeGen.Arm64
private const int CbnzInstLength = 4;
private const int LdrLitInstLength = 4;
private readonly Stream _stream;
private readonly RecyclableMemoryStream _stream;
public int StreamOffset => (int)_stream.Length;

13
src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs
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@@ -189,8 +189,8 @@ namespace ARMeilleure.CodeGen.Arm64
// The only blocks which can have 0 successors are exit blocks.
Operation last = block.Operations.Last;
Debug.Assert(last.Instruction == Instruction.Tailcall ||
last.Instruction == Instruction.Return);
Debug.Assert(last.Instruction is Instruction.Tailcall or
Instruction.Return);
}
else
{
@@ -464,7 +464,7 @@ namespace ARMeilleure.CodeGen.Arm64
Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type == OperandType.FP32 || dest.Type == OperandType.FP64);
Debug.Assert(dest.Type is OperandType.FP32 or OperandType.FP64);
Debug.Assert(dest.Type != source.Type);
Debug.Assert(source.Type != OperandType.V128);
@@ -483,7 +483,7 @@ namespace ARMeilleure.CodeGen.Arm64
Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type == OperandType.FP32 || dest.Type == OperandType.FP64);
Debug.Assert(dest.Type is OperandType.FP32 or OperandType.FP64);
Debug.Assert(dest.Type != source.Type);
Debug.Assert(source.Type.IsInteger());
@@ -1463,7 +1463,7 @@ namespace ARMeilleure.CodeGen.Arm64
private static bool IsLoadOrStore(Operation operation)
{
return operation.Instruction == Instruction.Load || operation.Instruction == Instruction.Store;
return operation.Instruction is Instruction.Load or Instruction.Store;
}
private static OperandType GetMemOpValueType(Operation operation)
@@ -1499,6 +1499,7 @@ namespace ARMeilleure.CodeGen.Arm64
return false;
}
}
if (memOp.Index != default)
{
return false;
@@ -1553,7 +1554,7 @@ namespace ARMeilleure.CodeGen.Arm64
private static void EnsureSameReg(Operand op1, Operand op2)
{
Debug.Assert(op1.Kind == OperandKind.Register || op1.Kind == OperandKind.Memory);
Debug.Assert(op1.Kind is OperandKind.Register or OperandKind.Memory);
Debug.Assert(op1.Kind == op2.Kind);
Debug.Assert(op1.Value == op2.Value);
}

1
src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs
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@@ -509,7 +509,6 @@ namespace ARMeilleure.CodeGen.Arm64
context.Assembler.WriteInstruction(instruction, rd, rn);
}
}
private static void GenerateScalarTernary(

1
src/ARMeilleure/CodeGen/Arm64/HardwareCapabilities.cs
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@@ -137,6 +137,7 @@ namespace ARMeilleure.CodeGen.Arm64
{
return val != 0;
}
return false;
}

34
src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs
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@@ -736,19 +736,19 @@ namespace ARMeilleure.CodeGen.Arm64
{
IntrinsicInfo info = IntrinsicTable.GetInfo(intrinsic & ~(Intrinsic.Arm64VTypeMask | Intrinsic.Arm64VSizeMask));
return info.Type == IntrinsicType.ScalarBinaryRd ||
info.Type == IntrinsicType.ScalarTernaryFPRdByElem ||
info.Type == IntrinsicType.ScalarTernaryShlRd ||
info.Type == IntrinsicType.ScalarTernaryShrRd ||
info.Type == IntrinsicType.Vector128BinaryRd ||
info.Type == IntrinsicType.VectorBinaryRd ||
info.Type == IntrinsicType.VectorInsertByElem ||
info.Type == IntrinsicType.VectorTernaryRd ||
info.Type == IntrinsicType.VectorTernaryRdBitwise ||
info.Type == IntrinsicType.VectorTernaryFPRdByElem ||
info.Type == IntrinsicType.VectorTernaryRdByElem ||
info.Type == IntrinsicType.VectorTernaryShlRd ||
info.Type == IntrinsicType.VectorTernaryShrRd;
return info.Type is IntrinsicType.ScalarBinaryRd or
IntrinsicType.ScalarTernaryFPRdByElem or
IntrinsicType.ScalarTernaryShlRd or
IntrinsicType.ScalarTernaryShrRd or
IntrinsicType.Vector128BinaryRd or
IntrinsicType.VectorBinaryRd or
IntrinsicType.VectorInsertByElem or
IntrinsicType.VectorTernaryRd or
IntrinsicType.VectorTernaryRdBitwise or
IntrinsicType.VectorTernaryFPRdByElem or
IntrinsicType.VectorTernaryRdByElem or
IntrinsicType.VectorTernaryShlRd or
IntrinsicType.VectorTernaryShrRd;
}
private static bool HasConstSrc1(Operation node, ulong value)
@@ -849,7 +849,7 @@ namespace ARMeilleure.CodeGen.Arm64
Comparison compType = (Comparison)comp.AsInt32();
return compType == Comparison.Equal || compType == Comparison.NotEqual;
return compType is Comparison.Equal or Comparison.NotEqual;
}
}
@@ -871,9 +871,9 @@ namespace ARMeilleure.CodeGen.Arm64
IntrinsicInfo info = IntrinsicTable.GetInfo(intrinsic & ~(Intrinsic.Arm64VTypeMask | Intrinsic.Arm64VSizeMask));
// Those have integer inputs that don't support consts.
return info.Type != IntrinsicType.ScalarFPConvGpr &&
info.Type != IntrinsicType.ScalarFPConvFixedGpr &&
info.Type != IntrinsicType.SetRegister;
return info.Type is not IntrinsicType.ScalarFPConvGpr and
not IntrinsicType.ScalarFPConvFixedGpr and
not IntrinsicType.SetRegister;
}
return false;