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Fix ~3500 analyser issues

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See merge request ryubing/ryujinx!44
This commit is contained in:
MrKev
2025-05-30 17:08:34 -05:00
committed by LotP
parent 417df486b1
commit 361d0c5632
622 changed files with 3080 additions and 2652 deletions
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2
src/Ryujinx.Cpu/LightningJit/Arm32/InstName.cs
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@@ -531,7 +531,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32
{
public static bool IsCall(this InstName name)
{
return name == InstName.BlI || name == InstName.BlxR;
return name is InstName.BlI or InstName.BlxR;
}
public static bool IsSystem(this InstName name)

2
src/Ryujinx.Cpu/LightningJit/Arm32/InstTableT32.cs
View File

@@ -526,7 +526,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32
new(0x00000041, 0x00000041)
];
List<InstInfoForTable> insts =
List<InstInfoForTable> insts =
[
new(0xF1400000, 0xFBE08000, InstName.AdcI, T.AdcIT1, IsaVersion.v80, InstFlags.Rd),
new(0xEB400000, 0xFFE08000, InstName.AdcR, T.AdcRT2, IsaVersion.v80, InstFlags.Rd),

5
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/Compiler.cs
View File

@@ -493,7 +493,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
{
delta = targetIndex - branchIndex;
if (delta >= -Encodable26BitsOffsetLimit && delta < Encodable26BitsOffsetLimit)
if (delta is >= (-Encodable26BitsOffsetLimit) and < Encodable26BitsOffsetLimit)
{
writer.WriteInstructionAt(branchIndex, encoding | (uint)(delta & 0x3ffffff));
@@ -559,7 +559,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
}
}
Debug.Assert(name == InstName.B || name == InstName.Cbnz, $"Unknown branch instruction \"{name}\".");
Debug.Assert(name is InstName.B or InstName.Cbnz, $"Unknown branch instruction \"{name}\".");
}
private static void RewriteCallInstructionWithTarget(in Context context, uint targetAddress, uint nextAddress, int branchIndex)
@@ -745,6 +745,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
InstEmitSystem.WriteUdf(context.Writer, context.RegisterAllocator, context.TailMerger, context.GetReservedStackOffset(), pc, imm);
break;
}
context.LoadFromContext();
break;
case BranchType.ReadCntpct:

1
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitAlu.cs
View File

@@ -736,6 +736,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
{
m = GetRrxC(context, dest, m, carryOut);
}
break;
}
}

2
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitFlow.cs
View File

@@ -142,7 +142,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
int tempRegister;
int tempGuestAddress = -1;
bool inlineLookup = guestAddress.Kind != OperandKind.Constant &&
bool inlineLookup = guestAddress.Kind != OperandKind.Constant &&
funcTable is { Sparse: true };
if (guestAddress.Kind == OperandKind.Constant)

30
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitNeonCommon.cs
View File

@@ -118,7 +118,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
public static void EmitScalarUnaryF(CodeGenContext context, uint rd, uint rm, uint size, Action<Operand, Operand, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@@ -133,7 +133,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
public static void EmitScalarUnaryF(CodeGenContext context, uint rd, uint rm, uint size, Action<Operand, Operand, uint> action, Action<Operand, Operand> actionHalf)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@@ -161,7 +161,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
uint sf,
Action<Operand, Operand, uint, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@@ -182,7 +182,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
uint sf,
Action<Operand, Operand, uint, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@@ -197,7 +197,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
public static void EmitScalarUnaryFixedF(CodeGenContext context, uint rd, uint rm, uint fbits, uint size, bool is16Bit, Action<Operand, Operand, uint, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@@ -214,7 +214,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
public static void EmitScalarBinaryF(CodeGenContext context, uint rd, uint rn, uint rm, uint size, Action<Operand, Operand, Operand, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@@ -252,7 +252,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
public static void EmitScalarTernaryRdF(CodeGenContext context, uint rd, uint rn, uint rm, uint size, Action<Operand, Operand, Operand, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@@ -276,7 +276,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
uint size,
Action<Operand, Operand, Operand, Operand, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@@ -300,7 +300,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
bool negD,
bool negProduct)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@@ -918,7 +918,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
Action<Operand, Operand, uint, uint> action,
Action<Operand, Operand, uint> actionHalf)
{
Debug.Assert(sz == 0 || sz == 1);
Debug.Assert(sz is 0 or 1);
if (q == 0)
{
@@ -962,7 +962,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
Action<Operand, Operand, uint, uint> action,
Action<Operand, Operand, uint> actionHalf)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
Debug.Assert(size != 3 || q == 1);
if (q == 0)
@@ -1007,7 +1007,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
uint q,
Action<Operand, Operand, uint, uint, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
Debug.Assert(size != 3 || q == 1);
(uint immb, uint immh) = GetImmbImmh(fbits, size);
@@ -1040,7 +1040,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
Action<Operand, Operand, Operand, uint, uint> action,
Action<Operand, Operand, Operand, uint> actionHalf)
{
Debug.Assert(sz == 0 || sz == 1);
Debug.Assert(sz is 0 or 1);
if (q == 0)
{
@@ -1100,7 +1100,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
Action<Operand, Operand, Operand, uint, uint> action,
Action<Operand, Operand, Operand, uint> actionHalf)
{
Debug.Assert(sz == 0 || sz == 1);
Debug.Assert(sz is 0 or 1);
if (q == 0)
{
@@ -1148,7 +1148,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
uint q,
bool negProduct)
{
Debug.Assert(sz == 0 || sz == 1);
Debug.Assert(sz is 0 or 1);
if (q == 0)
{

2
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitNeonMemory.cs
View File

@@ -467,7 +467,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
private static void EmitMemory1234InstructionCore(CodeGenContext context, uint rn, uint rm, int bytes, Action<Operand> callback)
{
bool wBack = rm != RegisterUtils.PcRegister;
bool registerIndex = rm != RegisterUtils.PcRegister && rm != RegisterUtils.SpRegister;
bool registerIndex = rm is not RegisterUtils.PcRegister and not RegisterUtils.SpRegister;
Operand rnOperand = InstEmitCommon.GetInputGpr(context, rn);

4
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitNeonMove.cs
View File

@@ -252,7 +252,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
}
else
{
Debug.Assert(opc1 == 0 || opc1 == 1);
Debug.Assert(opc1 is 0 or 1);
Debug.Assert(opc2 == 0);
index = opc1 & 1u;
@@ -307,7 +307,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
}
else
{
Debug.Assert(opc1 == 0 || opc1 == 1);
Debug.Assert(opc1 is 0 or 1);
Debug.Assert(opc2 == 0);
Debug.Assert(!u);

3
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitSystem.cs
View File

@@ -60,6 +60,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
return;
}
}
break;
}
}
@@ -109,6 +110,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
break;
}
}
break;
}
@@ -142,6 +144,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
context.Arm64Assembler.B(0);
return;
}
break;
}

2
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitVfpCompare.cs
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@@ -27,7 +27,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
private static void EmitVcmpVcmpe(CodeGenContext context, uint cond, uint rd, uint rm, uint size, bool zero, bool e)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
uint ftype = size ^ 2u;

2
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitVfpConvert.cs
View File

@@ -231,7 +231,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
{
bool unsigned = (op & 1) == 0;
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;