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Implement a new JIT for Arm devices (#6057)
* Implement a new JIT for Arm devices * Auto-format * Make a lot of Assembler members read-only * More read-only * Fix more warnings * ObjectDisposedException.ThrowIf * New JIT cache for platforms that enforce W^X, currently unused * Remove unused using * Fix assert * Pass memory manager type around * Safe memory manager mode support + other improvements * Actual safe memory manager mode masking support * PR feedback
This commit is contained in:
gdkchan
GitHub
@@ -0,0 +1,610 @@
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using ARMeilleure.Common;
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using Ryujinx.Cpu.LightningJit.CodeGen;
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using Ryujinx.Cpu.LightningJit.CodeGen.Arm64;
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using System;
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using System.Diagnostics;
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using System.Numerics;
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using System.Runtime.CompilerServices;
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using System.Runtime.InteropServices;
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namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
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{
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static class InstEmitSystem
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{
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private delegate void SoftwareInterruptHandler(ulong address, int imm);
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private delegate ulong Get64();
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private delegate bool GetBool();
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public static void RewriteInstruction(
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CodeWriter writer,
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RegisterAllocator regAlloc,
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TailMerger tailMerger,
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InstName name,
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ulong pc,
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uint encoding,
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int spillBaseOffset)
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{
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if (name == InstName.Brk)
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{
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Assembler asm = new(writer);
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WriteCall(ref asm, regAlloc, GetBrkHandlerPtr(), spillBaseOffset, null, pc, encoding);
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WriteSyncPoint(writer, ref asm, regAlloc, tailMerger, spillBaseOffset);
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}
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else if (name == InstName.Svc)
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{
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uint svcId = (ushort)(encoding >> 5);
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Assembler asm = new(writer);
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WriteCall(ref asm, regAlloc, GetSvcHandlerPtr(), spillBaseOffset, null, pc, svcId);
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WriteSyncPoint(writer, ref asm, regAlloc, tailMerger, spillBaseOffset);
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}
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else if (name == InstName.UdfPermUndef)
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{
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Assembler asm = new(writer);
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WriteCall(ref asm, regAlloc, GetUdfHandlerPtr(), spillBaseOffset, null, pc, encoding);
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WriteSyncPoint(writer, ref asm, regAlloc, tailMerger, spillBaseOffset);
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}
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else if ((encoding & ~0x1f) == 0xd53bd060) // mrs x0, tpidrro_el0
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{
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uint rd = encoding & 0x1f;
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if (rd != RegisterUtils.ZrIndex)
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{
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Assembler asm = new(writer);
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asm.LdrRiUn(Register((int)rd), Register(regAlloc.FixedContextRegister), NativeContextOffsets.TpidrroEl0Offset);
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}
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}
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else if ((encoding & ~0x1f) == 0xd53bd040) // mrs x0, tpidr_el0
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{
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uint rd = encoding & 0x1f;
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if (rd != RegisterUtils.ZrIndex)
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{
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Assembler asm = new(writer);
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asm.LdrRiUn(Register((int)rd), Register(regAlloc.FixedContextRegister), NativeContextOffsets.TpidrEl0Offset);
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}
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}
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else if ((encoding & ~0x1f) == 0xd53b0020 && IsAppleOS()) // mrs x0, ctr_el0
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{
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uint rd = encoding & 0x1f;
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if (rd != RegisterUtils.ZrIndex)
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{
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Assembler asm = new(writer);
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// TODO: Use host value? But that register can't be accessed on macOS...
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asm.Mov(Register((int)rd, OperandType.I32), 0x8444c004);
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}
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}
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else if ((encoding & ~0x1f) == 0xd53be020) // mrs x0, cntpct_el0
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{
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uint rd = encoding & 0x1f;
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if (rd != RegisterUtils.ZrIndex)
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{
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Assembler asm = new(writer);
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WriteCall(ref asm, regAlloc, GetCntpctEl0Ptr(), spillBaseOffset, (int)rd);
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}
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}
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else if ((encoding & ~0x1f) == 0xd51bd040) // msr tpidr_el0, x0
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{
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uint rd = encoding & 0x1f;
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if (rd != RegisterUtils.ZrIndex)
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{
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Assembler asm = new(writer);
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asm.StrRiUn(Register((int)rd), Register(regAlloc.FixedContextRegister), NativeContextOffsets.TpidrEl0Offset);
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}
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}
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else
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{
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writer.WriteInstruction(encoding);
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}
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}
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public static bool NeedsCall(uint encoding)
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{
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if ((encoding & ~(0xffffu << 5)) == 0xd4000001u) // svc #0
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{
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return true;
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}
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else if ((encoding & ~0x1f) == 0xd53b0020 && IsAppleOS()) // mrs x0, ctr_el0
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{
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return true;
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}
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else if ((encoding & ~0x1f) == 0xd53be020) // mrs x0, cntpct_el0
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{
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return true;
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}
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return false;
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}
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private static bool IsAppleOS()
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{
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return OperatingSystem.IsMacOS() || OperatingSystem.IsIOS();
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}
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public static bool NeedsContextStoreLoad(InstName name)
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{
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return name == InstName.Svc;
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}
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private static IntPtr GetBrkHandlerPtr()
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{
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return Marshal.GetFunctionPointerForDelegate<SoftwareInterruptHandler>(NativeInterface.Break);
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}
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private static IntPtr GetSvcHandlerPtr()
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{
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return Marshal.GetFunctionPointerForDelegate<SoftwareInterruptHandler>(NativeInterface.SupervisorCall);
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}
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private static IntPtr GetUdfHandlerPtr()
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{
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return Marshal.GetFunctionPointerForDelegate<SoftwareInterruptHandler>(NativeInterface.Undefined);
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}
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private static IntPtr GetCntpctEl0Ptr()
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{
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return Marshal.GetFunctionPointerForDelegate<Get64>(NativeInterface.GetCntpctEl0);
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}
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private static IntPtr CheckSynchronizationPtr()
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{
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return Marshal.GetFunctionPointerForDelegate<GetBool>(NativeInterface.CheckSynchronization);
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}
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public static void WriteSyncPoint(CodeWriter writer, RegisterAllocator regAlloc, TailMerger tailMerger, int spillBaseOffset)
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{
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Assembler asm = new(writer);
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WriteSyncPoint(writer, ref asm, regAlloc, tailMerger, spillBaseOffset);
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}
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private static void WriteSyncPoint(CodeWriter writer, ref Assembler asm, RegisterAllocator regAlloc, TailMerger tailMerger, int spillBaseOffset)
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{
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int tempRegister = regAlloc.AllocateTempGprRegister();
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Operand rt = Register(tempRegister, OperandType.I32);
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asm.LdrRiUn(rt, Register(regAlloc.FixedContextRegister), NativeContextOffsets.CounterOffset);
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int branchIndex = writer.InstructionPointer;
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asm.Cbnz(rt, 0);
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WriteSpill(ref asm, regAlloc, 1u << tempRegister, spillBaseOffset, tempRegister);
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Operand rn = Register(tempRegister == 0 ? 1 : 0);
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asm.Mov(rn, (ulong)CheckSynchronizationPtr());
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asm.Blr(rn);
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tailMerger.AddConditionalZeroReturn(writer, asm, Register(0, OperandType.I32));
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WriteFill(ref asm, regAlloc, 1u << tempRegister, spillBaseOffset, tempRegister);
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asm.LdrRiUn(rt, Register(regAlloc.FixedContextRegister), NativeContextOffsets.CounterOffset);
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uint branchInst = writer.ReadInstructionAt(branchIndex);
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writer.WriteInstructionAt(branchIndex, branchInst | (((uint)(writer.InstructionPointer - branchIndex) & 0x7ffff) << 5));
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asm.Sub(rt, rt, new Operand(OperandKind.Constant, OperandType.I32, 1));
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asm.StrRiUn(rt, Register(regAlloc.FixedContextRegister), NativeContextOffsets.CounterOffset);
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regAlloc.FreeTempGprRegister(tempRegister);
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}
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public static void RewriteCallInstruction(
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CodeWriter writer,
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RegisterAllocator regAlloc,
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TailMerger tailMerger,
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Action writeEpilogue,
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AddressTable<ulong> funcTable,
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IntPtr dispatchStubPtr,
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InstName name,
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ulong pc,
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uint encoding,
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int spillBaseOffset,
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bool isTail = false)
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{
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Assembler asm = new(writer);
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switch (name)
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{
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case InstName.BUncond:
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case InstName.Bl:
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case InstName.Blr:
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case InstName.Br:
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if (name == InstName.BUncond || name == InstName.Bl)
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{
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int imm = ImmUtils.ExtractSImm26Times4(encoding);
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WriteCallWithGuestAddress(
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writer,
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ref asm,
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regAlloc,
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tailMerger,
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writeEpilogue,
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funcTable,
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dispatchStubPtr,
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spillBaseOffset,
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pc,
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new(OperandKind.Constant, OperandType.I64, pc + (ulong)imm),
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isTail);
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}
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else
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{
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int rnIndex = RegisterUtils.ExtractRn(encoding);
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if (rnIndex == RegisterUtils.ZrIndex)
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{
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WriteCallWithGuestAddress(
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writer,
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ref asm,
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regAlloc,
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tailMerger,
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writeEpilogue,
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funcTable,
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dispatchStubPtr,
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spillBaseOffset,
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pc,
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new(OperandKind.Constant, OperandType.I64, 0UL),
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isTail);
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}
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else
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{
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rnIndex = regAlloc.RemapReservedGprRegister(rnIndex);
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WriteCallWithGuestAddress(
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writer,
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ref asm,
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regAlloc,
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tailMerger,
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writeEpilogue,
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funcTable,
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dispatchStubPtr,
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spillBaseOffset,
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pc,
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Register(rnIndex),
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isTail);
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}
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}
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break;
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default:
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Debug.Fail($"Unknown branch instruction \"{name}\".");
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break;
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}
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}
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public unsafe static void WriteCallWithGuestAddress(
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CodeWriter writer,
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ref Assembler asm,
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RegisterAllocator regAlloc,
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TailMerger tailMerger,
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Action writeEpilogue,
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AddressTable<ulong> funcTable,
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IntPtr funcPtr,
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int spillBaseOffset,
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ulong pc,
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Operand guestAddress,
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bool isTail = false)
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{
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int tempRegister;
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if (guestAddress.Kind == OperandKind.Constant)
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{
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tempRegister = regAlloc.AllocateTempGprRegister();
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asm.Mov(Register(tempRegister), guestAddress.Value);
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asm.StrRiUn(Register(tempRegister), Register(regAlloc.FixedContextRegister), NativeContextOffsets.DispatchAddressOffset);
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regAlloc.FreeTempGprRegister(tempRegister);
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}
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else
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{
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asm.StrRiUn(guestAddress, Register(regAlloc.FixedContextRegister), NativeContextOffsets.DispatchAddressOffset);
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}
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tempRegister = regAlloc.FixedContextRegister == 1 ? 2 : 1;
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if (!isTail)
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{
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WriteSpillSkipContext(ref asm, regAlloc, spillBaseOffset);
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}
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Operand rn = Register(tempRegister);
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if (regAlloc.FixedContextRegister != 0)
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{
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asm.Mov(Register(0), Register(regAlloc.FixedContextRegister));
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}
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if (guestAddress.Kind == OperandKind.Constant && funcTable != null)
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{
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ulong funcPtrLoc = (ulong)Unsafe.AsPointer(ref funcTable.GetValue(guestAddress.Value));
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asm.Mov(rn, funcPtrLoc & ~0xfffUL);
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asm.LdrRiUn(rn, rn, (int)(funcPtrLoc & 0xfffUL));
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}
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else
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{
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asm.Mov(rn, (ulong)funcPtr);
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}
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if (isTail)
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{
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writeEpilogue();
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asm.Br(rn);
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}
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else
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{
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asm.Blr(rn);
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ulong nextAddress = pc + 4UL;
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asm.Mov(rn, nextAddress);
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asm.Cmp(Register(0), rn);
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tailMerger.AddConditionalReturn(writer, asm, ArmCondition.Ne);
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WriteFillSkipContext(ref asm, regAlloc, spillBaseOffset);
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}
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}
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private static void WriteCall(
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ref Assembler asm,
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RegisterAllocator regAlloc,
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IntPtr funcPtr,
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int spillBaseOffset,
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int? resultRegister,
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params ulong[] callArgs)
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{
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uint resultMask = 0u;
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if (resultRegister.HasValue)
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{
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resultMask = 1u << resultRegister.Value;
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}
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int tempRegister = callArgs.Length;
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if (resultRegister.HasValue && tempRegister == resultRegister.Value)
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{
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tempRegister++;
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}
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WriteSpill(ref asm, regAlloc, resultMask, spillBaseOffset, tempRegister);
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// We only support up to 7 arguments right now.
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// ABI defines the first 8 integer arguments to be passed on registers X0-X7.
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// We need at least one register to put the function address on, so that reduces the number of
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// registers we can use for that by one.
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Debug.Assert(callArgs.Length < 8);
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for (int index = 0; index < callArgs.Length; index++)
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{
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asm.Mov(Register(index), callArgs[index]);
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}
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Operand rn = Register(tempRegister);
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asm.Mov(rn, (ulong)funcPtr);
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asm.Blr(rn);
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if (resultRegister.HasValue && resultRegister.Value != 0)
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{
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asm.Mov(Register(resultRegister.Value), Register(0));
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}
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WriteFill(ref asm, regAlloc, resultMask, spillBaseOffset, tempRegister);
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}
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private static void WriteSpill(ref Assembler asm, RegisterAllocator regAlloc, uint exceptMask, int spillOffset, int tempRegister)
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{
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WriteSpillOrFill(ref asm, regAlloc, exceptMask, spillOffset, tempRegister, spill: true);
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}
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private static void WriteFill(ref Assembler asm, RegisterAllocator regAlloc, uint exceptMask, int spillOffset, int tempRegister)
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{
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WriteSpillOrFill(ref asm, regAlloc, exceptMask, spillOffset, tempRegister, spill: false);
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}
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private static void WriteSpillOrFill(
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ref Assembler asm,
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RegisterAllocator regAlloc,
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uint exceptMask,
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int spillOffset,
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int tempRegister,
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bool spill)
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{
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uint gprMask = regAlloc.AllGprMask & ~(AbiConstants.GprCalleeSavedRegsMask | exceptMask);
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if (regAlloc.AllPStateMask != 0 && !spill)
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{
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// We must reload the status register before reloading the GPRs,
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// since we might otherwise trash one of them by using it as temp register.
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Operand rt = Register(tempRegister, OperandType.I32);
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asm.LdrRiUn(rt, Register(RegisterUtils.SpIndex), spillOffset + BitOperations.PopCount(gprMask) * 8);
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asm.MsrNzcv(rt);
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}
|
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|
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while (gprMask != 0)
|
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{
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int reg = BitOperations.TrailingZeroCount(gprMask);
|
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|
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if (reg < 31 && (gprMask & (2u << reg)) != 0 && spillOffset < RegisterSaveRestore.Encodable9BitsOffsetLimit)
|
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{
|
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if (spill)
|
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{
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asm.StpRiUn(
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Register(regAlloc.RemapReservedGprRegister(reg)),
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Register(regAlloc.RemapReservedGprRegister(reg + 1)),
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Register(RegisterUtils.SpIndex),
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spillOffset);
|
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}
|
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else
|
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{
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asm.LdpRiUn(
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Register(regAlloc.RemapReservedGprRegister(reg)),
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Register(regAlloc.RemapReservedGprRegister(reg + 1)),
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Register(RegisterUtils.SpIndex),
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spillOffset);
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}
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gprMask &= ~(3u << reg);
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spillOffset += 16;
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}
|
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else
|
||||
{
|
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if (spill)
|
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{
|
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asm.StrRiUn(Register(regAlloc.RemapReservedGprRegister(reg)), Register(RegisterUtils.SpIndex), spillOffset);
|
||||
}
|
||||
else
|
||||
{
|
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asm.LdrRiUn(Register(regAlloc.RemapReservedGprRegister(reg)), Register(RegisterUtils.SpIndex), spillOffset);
|
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}
|
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|
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gprMask &= ~(1u << reg);
|
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spillOffset += 8;
|
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}
|
||||
}
|
||||
|
||||
if (regAlloc.AllPStateMask != 0)
|
||||
{
|
||||
if (spill)
|
||||
{
|
||||
Operand rt = Register(tempRegister, OperandType.I32);
|
||||
|
||||
asm.MrsNzcv(rt);
|
||||
asm.StrRiUn(rt, Register(RegisterUtils.SpIndex), spillOffset);
|
||||
}
|
||||
|
||||
spillOffset += 8;
|
||||
}
|
||||
|
||||
if ((spillOffset & 8) != 0)
|
||||
{
|
||||
spillOffset += 8;
|
||||
}
|
||||
|
||||
uint fpSimdMask = regAlloc.AllFpSimdMask;
|
||||
|
||||
while (fpSimdMask != 0)
|
||||
{
|
||||
int reg = BitOperations.TrailingZeroCount(fpSimdMask);
|
||||
|
||||
if (reg < 31 && (fpSimdMask & (2u << reg)) != 0 && spillOffset < RegisterSaveRestore.Encodable9BitsOffsetLimit)
|
||||
{
|
||||
if (spill)
|
||||
{
|
||||
asm.StpRiUn(
|
||||
Register(reg, OperandType.V128),
|
||||
Register(reg + 1, OperandType.V128),
|
||||
Register(RegisterUtils.SpIndex),
|
||||
spillOffset);
|
||||
}
|
||||
else
|
||||
{
|
||||
asm.LdpRiUn(
|
||||
Register(reg, OperandType.V128),
|
||||
Register(reg + 1, OperandType.V128),
|
||||
Register(RegisterUtils.SpIndex),
|
||||
spillOffset);
|
||||
}
|
||||
|
||||
fpSimdMask &= ~(3u << reg);
|
||||
spillOffset += 32;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (spill)
|
||||
{
|
||||
asm.StrRiUn(Register(reg, OperandType.V128), Register(RegisterUtils.SpIndex), spillOffset);
|
||||
}
|
||||
else
|
||||
{
|
||||
asm.LdrRiUn(Register(reg, OperandType.V128), Register(RegisterUtils.SpIndex), spillOffset);
|
||||
}
|
||||
|
||||
fpSimdMask &= ~(1u << reg);
|
||||
spillOffset += 16;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
private static void WriteSpillSkipContext(ref Assembler asm, RegisterAllocator regAlloc, int spillOffset)
|
||||
{
|
||||
WriteSpillOrFillSkipContext(ref asm, regAlloc, spillOffset, spill: true);
|
||||
}
|
||||
|
||||
private static void WriteFillSkipContext(ref Assembler asm, RegisterAllocator regAlloc, int spillOffset)
|
||||
{
|
||||
WriteSpillOrFillSkipContext(ref asm, regAlloc, spillOffset, spill: false);
|
||||
}
|
||||
|
||||
private static void WriteSpillOrFillSkipContext(ref Assembler asm, RegisterAllocator regAlloc, int spillOffset, bool spill)
|
||||
{
|
||||
uint gprMask = regAlloc.AllGprMask & ((1u << regAlloc.FixedContextRegister) | (1u << regAlloc.FixedPageTableRegister));
|
||||
gprMask &= ~AbiConstants.GprCalleeSavedRegsMask;
|
||||
|
||||
while (gprMask != 0)
|
||||
{
|
||||
int reg = BitOperations.TrailingZeroCount(gprMask);
|
||||
|
||||
if (reg < 31 && (gprMask & (2u << reg)) != 0 && spillOffset < RegisterSaveRestore.Encodable9BitsOffsetLimit)
|
||||
{
|
||||
if (spill)
|
||||
{
|
||||
asm.StpRiUn(
|
||||
Register(regAlloc.RemapReservedGprRegister(reg)),
|
||||
Register(regAlloc.RemapReservedGprRegister(reg + 1)),
|
||||
Register(RegisterUtils.SpIndex),
|
||||
spillOffset);
|
||||
}
|
||||
else
|
||||
{
|
||||
asm.LdpRiUn(
|
||||
Register(regAlloc.RemapReservedGprRegister(reg)),
|
||||
Register(regAlloc.RemapReservedGprRegister(reg + 1)),
|
||||
Register(RegisterUtils.SpIndex),
|
||||
spillOffset);
|
||||
}
|
||||
|
||||
gprMask &= ~(3u << reg);
|
||||
spillOffset += 16;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (spill)
|
||||
{
|
||||
asm.StrRiUn(Register(regAlloc.RemapReservedGprRegister(reg)), Register(RegisterUtils.SpIndex), spillOffset);
|
||||
}
|
||||
else
|
||||
{
|
||||
asm.LdrRiUn(Register(regAlloc.RemapReservedGprRegister(reg)), Register(RegisterUtils.SpIndex), spillOffset);
|
||||
}
|
||||
|
||||
gprMask &= ~(1u << reg);
|
||||
spillOffset += 8;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
private static Operand Register(int register, OperandType type = OperandType.I64)
|
||||
{
|
||||
return new Operand(register, RegisterType.Integer, type);
|
||||
}
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user