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feature: .NET 10 (ryubing/ryujinx!214)

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See merge request ryubing/ryujinx!214
This commit is contained in:
GreemDev
2025-11-11 12:55:36 -06:00
parent 49c70efdd5
commit 6b814fb973
171 changed files with 6011 additions and 6335 deletions
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2
src/Ryujinx.Cpu/Jit/JitCpuContext.cs
View File

@@ -17,7 +17,7 @@ namespace Ryujinx.Cpu.Jit
_functionTable = AddressTable<ulong>.CreateForArm(for64Bit, memory.Type);
_translator = new Translator(new JitMemoryAllocator(forJit: true), memory, _functionTable);
if (memory.Type.IsHostMappedOrTracked())
if (memory.Type.IsHostMappedOrTracked)
{
NativeSignalHandler.InitializeSignalHandler();
}

2
src/Ryujinx.Cpu/LightningJit/Arm32/ScopedRegister.cs
View File

@@ -26,7 +26,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32
return;
}
if (_operand.Type.IsInteger())
if (_operand.Type.IsInteger)
{
_registerAllocator.FreeTempGprRegister(_operand.AsInt32());
}

2
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/Compiler.cs
View File

@@ -381,7 +381,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
if (currentCond != ArmCondition.Al)
{
instructionPointer = context.CodeWriter.InstructionPointer;
context.Arm64Assembler.B(currentCond.Invert(), 0);
context.Arm64Assembler.B(currentCond.Inverse, 0);
}
}
}

2
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitFlow.cs
View File

@@ -104,7 +104,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
if (invert)
{
conditions[i++] = ((ArmCondition)firstCond).Invert();
conditions[i++] = ((ArmCondition)firstCond).Inverse;
}
else
{

4
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitMemory.cs
View File

@@ -1129,7 +1129,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
// We don't need to mask the address for the safe mode, since it is already naturally limited to 32-bit
// and can never reach out of the guest address space.
if (mmType.IsHostTracked())
if (mmType.IsHostTracked)
{
int tempRegister = regAlloc.AllocateTempGprRegister();
@@ -1141,7 +1141,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
regAlloc.FreeTempGprRegister(tempRegister);
}
else if (mmType.IsHostMapped())
else if (mmType.IsHostMapped)
{
asm.Add(destination64, basePointer, guestAddress);
}

2
src/Ryujinx.Cpu/LightningJit/Arm64/Block.cs
View File

@@ -132,7 +132,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64
InstName lastInstructionName = Instructions[^1].Name;
return lastInstructionName.IsCall() || lastInstructionName.IsException();
return lastInstructionName.IsCall || lastInstructionName.IsException;
}
}
}

139
src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs
View File

@@ -1042,126 +1042,39 @@ namespace Ryujinx.Cpu.LightningJit.Arm64
static class InstNameExtensions
{
public static bool IsCall(this InstName name)
extension(InstName name)
{
return name is InstName.Bl or InstName.Blr;
}
public bool IsCall => name is InstName.Bl or InstName.Blr;
public static bool IsControlFlowOrException(this InstName name)
{
switch (name)
public bool IsControlFlowOrException => name is
InstName.BUncond or InstName.BCond or InstName.Bl or InstName.Blr or InstName.Br or InstName.Brk
or InstName.Cbnz or InstName.Cbz or InstName.Ret or InstName.Tbnz or InstName.Tbz or InstName.Svc
or InstName.UdfPermUndef;
public bool IsException => name is InstName.Brk or InstName.Svc or InstName.UdfPermUndef;
public bool IsSystem => name switch
{
case InstName.BUncond:
case InstName.BCond:
case InstName.Bl:
case InstName.Blr:
case InstName.Br:
case InstName.Brk:
case InstName.Cbnz:
case InstName.Cbz:
case InstName.Ret:
case InstName.Tbnz:
case InstName.Tbz:
case InstName.Svc:
case InstName.UdfPermUndef:
return true;
}
InstName.Mrs or InstName.MsrImm or InstName.MsrReg => true,
_ => name.IsException
};
return false;
}
public bool IsSystemOrCall => name.IsCall || name is
InstName.Svc or InstName.Mrs or InstName.MsrImm or InstName.MsrReg
or InstName.Sysl;
public static bool IsException(this InstName name)
{
switch (name)
{
case InstName.Brk:
case InstName.Svc:
case InstName.UdfPermUndef:
return true;
}
public bool IsPrivileged => name is
InstName.Dcps1 or InstName.Dcps2 or InstName.Dcps3 or InstName.Drps or InstName.Eret or InstName.Ereta
or InstName.Hvc or InstName.MsrImm or InstName.Smc;
return false;
}
public bool IsPartialRegisterUpdateMemory => name is
InstName.Ld1AdvsimdSnglAsNoPostIndex or InstName.Ld1AdvsimdSnglAsPostIndex
or InstName.Ld2AdvsimdSnglAsNoPostIndex or InstName.Ld2AdvsimdSnglAsPostIndex
or InstName.Ld3AdvsimdSnglAsNoPostIndex or InstName.Ld3AdvsimdSnglAsPostIndex
or InstName.Ld4AdvsimdSnglAsNoPostIndex or InstName.Ld4AdvsimdSnglAsPostIndex;
public static bool IsSystem(this InstName name)
{
switch (name)
{
case InstName.Mrs:
case InstName.MsrImm:
case InstName.MsrReg:
return true;
}
return name.IsException();
}
public static bool IsSystemOrCall(this InstName name)
{
switch (name)
{
case InstName.Bl:
case InstName.Blr:
case InstName.Svc:
case InstName.Mrs:
case InstName.MsrImm:
case InstName.MsrReg:
case InstName.Sysl:
return true;
}
return false;
}
public static bool IsPrivileged(this InstName name)
{
switch (name)
{
case InstName.Dcps1:
case InstName.Dcps2:
case InstName.Dcps3:
case InstName.Drps:
case InstName.Eret:
case InstName.Ereta:
case InstName.Hvc:
case InstName.MsrImm:
case InstName.Smc:
return true;
}
return false;
}
public static bool IsPartialRegisterUpdateMemory(this InstName name)
{
switch (name)
{
case InstName.Ld1AdvsimdSnglAsNoPostIndex:
case InstName.Ld1AdvsimdSnglAsPostIndex:
case InstName.Ld2AdvsimdSnglAsNoPostIndex:
case InstName.Ld2AdvsimdSnglAsPostIndex:
case InstName.Ld3AdvsimdSnglAsNoPostIndex:
case InstName.Ld3AdvsimdSnglAsPostIndex:
case InstName.Ld4AdvsimdSnglAsNoPostIndex:
case InstName.Ld4AdvsimdSnglAsPostIndex:
return true;
}
return false;
}
public static bool IsPrefetchMemory(this InstName name)
{
switch (name)
{
case InstName.PrfmImm:
case InstName.PrfmLit:
case InstName.PrfmReg:
case InstName.Prfum:
return true;
}
return false;
public bool IsPrefetchMemory => name is
InstName.PrfmImm or InstName.PrfmLit or InstName.PrfmReg or InstName.Prfum;
}
}
}

2
src/Ryujinx.Cpu/LightningJit/Arm64/RegisterAllocator.cs
View File

@@ -150,7 +150,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64
public static int CalculateMaxTemps(MemoryManagerType mmType)
{
return mmType.IsHostMapped() ? 1 : 2;
return mmType.IsHostMapped ? 1 : 2;
}
public static int CalculateMaxTempsInclFixed(MemoryManagerType mmType)

4
src/Ryujinx.Cpu/LightningJit/Arm64/RegisterUtils.cs
View File

@@ -247,7 +247,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64
}
}
if (!flags.HasFlag(InstFlags.ReadRt) || name.IsPartialRegisterUpdateMemory())
if (!flags.HasFlag(InstFlags.ReadRt) || name.IsPartialRegisterUpdateMemory)
{
if (flags.HasFlag(InstFlags.Rt))
{
@@ -281,7 +281,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64
gprMask |= MaskFromIndex(ExtractRd(flags, encoding));
}
if (!flags.HasFlag(InstFlags.ReadRt) || name.IsPartialRegisterUpdateMemory())
if (!flags.HasFlag(InstFlags.ReadRt) || name.IsPartialRegisterUpdateMemory)
{
if (flags.HasFlag(InstFlags.Rt))
{

4
src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/Compiler.cs
View File

@@ -364,7 +364,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
{
InstEmitMemory.RewriteSysInstruction(memoryManager.AddressSpaceBits, memoryManager.Type, writer, regAlloc, encoding);
}
else if (instInfo.Name.IsSystem())
else if (instInfo.Name.IsSystem)
{
bool needsContextStoreLoad = InstEmitSystem.NeedsContextStoreLoad(instInfo.Name);
@@ -405,7 +405,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
lastInstructionEncoding = RegisterUtils.RemapRegisters(regAlloc, lastInstructionFlags, lastInstructionEncoding);
if (lastInstructionName.IsCall())
if (lastInstructionName.IsCall)
{
context.StoreToContextBeforeCall(blockIndex, pc + 4UL);

12
src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/Decoder.cs
View File

@@ -257,7 +257,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
(name, flags, AddressForm addressForm) = InstTable.GetInstNameAndFlags(encoding, cpuPreset.Version, cpuPreset.Features);
if (name.IsPrivileged() || (name == InstName.Sys && IsPrivilegedSys(encoding)))
if (name.IsPrivileged || (name == InstName.Sys && IsPrivilegedSys(encoding)))
{
name = InstName.UdfPermUndef;
flags = InstFlags.None;
@@ -267,7 +267,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
(uint instGprReadMask, uint instFpSimdReadMask) = RegisterUtils.PopulateReadMasks(name, flags, encoding);
(uint instGprWriteMask, uint instFpSimdWriteMask) = RegisterUtils.PopulateWriteMasks(name, flags, encoding);
if (name.IsCall())
if (name.IsCall)
{
instGprWriteMask |= 1u << RegisterUtils.LrIndex;
}
@@ -310,12 +310,12 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
fpSimdUseMask |= instFpSimdReadMask | instFpSimdWriteMask;
pStateUseMask |= instPStateReadMask | instPStateWriteMask;
if (name.IsSystemOrCall() && !hasHostCall)
if (name.IsSystemOrCall && !hasHostCall)
{
hasHostCall = name.IsCall() || InstEmitSystem.NeedsCall(encoding);
hasHostCall = name.IsCall || InstEmitSystem.NeedsCall(encoding);
}
isControlFlow = name.IsControlFlowOrException();
isControlFlow = name.IsControlFlowOrException;
RegisterUse registerUse = new(
instGprReadMask,
@@ -339,7 +339,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
useMask = new(gprUseMask, fpSimdUseMask, pStateUseMask);
return new(startAddress, address, insts, !isTruncated && !name.IsException(), isTruncated, isLoopEnd);
return new(startAddress, address, insts, !isTruncated && !name.IsException, isTruncated, isLoopEnd);
}
private static bool IsPrivilegedSys(uint encoding)

6
src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/InstEmitMemory.cs
View File

@@ -55,7 +55,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
ulong pc,
uint encoding)
{
if (name.IsPrefetchMemory() && mmType == MemoryManagerType.HostTrackedUnsafe)
if (name.IsPrefetchMemory && mmType == MemoryManagerType.HostTrackedUnsafe)
{
// Prefetch to invalid addresses do not cause faults, so for memory manager
// types where we need to access the page table before doing the prefetch,
@@ -544,7 +544,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
{
Operand basePointer = new(regAlloc.FixedPageTableRegister, RegisterType.Integer, OperandType.I64);
if (mmType.IsHostTracked())
if (mmType.IsHostTracked)
{
int tempRegister = regAlloc.AllocateTempGprRegister();
@@ -562,7 +562,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
regAlloc.FreeTempGprRegister(tempRegister);
}
else if (mmType.IsHostMapped())
else if (mmType.IsHostMapped)
{
if (mmType == MemoryManagerType.HostMapped)
{

4
src/Ryujinx.Cpu/LightningJit/CodeGen/Arm64/ArmCondition.cs
View File

@@ -22,9 +22,9 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
static class ArmConditionExtensions
{
public static ArmCondition Invert(this ArmCondition condition)
extension(ArmCondition condition)
{
return (ArmCondition)((int)condition ^ 1);
public ArmCondition Inverse => (ArmCondition)((int)condition ^ 1);
}
}
}

8
src/Ryujinx.Cpu/LightningJit/CodeGen/Arm64/Assembler.cs
View File

@@ -673,7 +673,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
public readonly void Mov(Operand rd, Operand rn)
{
Debug.Assert(rd.Type.IsInteger());
Debug.Assert(rd.Type.IsInteger);
Orr(rd, new Operand(ZrRegister, RegisterType.Integer, rd.Type), rn);
}
@@ -4544,7 +4544,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
uint instruction;
int scale;
if (type.IsInteger())
if (type.IsInteger)
{
instruction = intInst;
@@ -4580,7 +4580,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
{
uint instruction;
if (type.IsInteger())
if (type.IsInteger)
{
instruction = intInst;
@@ -4610,7 +4610,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
{
uint instruction;
if (type.IsInteger())
if (type.IsInteger)
{
instruction = intInst;

14
src/Ryujinx.Cpu/LightningJit/CodeGen/Arm64/RegisterSaveRestore.cs
View File

@@ -34,7 +34,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
int gprCalleeSavedRegsCount = BitOperations.PopCount(_gprMask);
int fpSimdCalleeSavedRegsCount = BitOperations.PopCount(_fpSimdMask);
return (_hasCall ? 16 : 0) + Align16(gprCalleeSavedRegsCount * 8 + fpSimdCalleeSavedRegsCount * _fpSimdType.GetSizeInBytes());
return (_hasCall ? 16 : 0) + Align16(gprCalleeSavedRegsCount * 8 + fpSimdCalleeSavedRegsCount * _fpSimdType.ByteSize);
}
public void WritePrologue(ref Assembler asm)
@@ -46,7 +46,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
int fpSimdCalleeSavedRegsCount = BitOperations.PopCount(fpSimdMask);
int reservedStackSize = Align16(_reservedStackSize);
int calleeSaveRegionSize = Align16(gprCalleeSavedRegsCount * 8 + fpSimdCalleeSavedRegsCount * _fpSimdType.GetSizeInBytes()) + reservedStackSize;
int calleeSaveRegionSize = Align16(gprCalleeSavedRegsCount * 8 + fpSimdCalleeSavedRegsCount * _fpSimdType.ByteSize) + reservedStackSize;
int offset = 0;
WritePrologueCalleeSavesPreIndexed(ref asm, ref gprMask, ref offset, calleeSaveRegionSize, OperandType.I64);
@@ -103,7 +103,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
asm.StrRiUn(Register(reg, type), Register(Assembler.SpRegister), 0);
}
offset += type.GetSizeInBytes();
offset += type.ByteSize;
}
while (mask != 0)
@@ -130,7 +130,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
asm.StpRiUn(Register(reg, type), Register(reg2, type), Register(Assembler.SpRegister), 0);
}
offset += type.GetSizeInBytes() * 2;
offset += type.ByteSize * 2;
}
}
@@ -144,7 +144,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
bool misalignedVector = _fpSimdType == OperandType.V128 && (gprCalleeSavedRegsCount & 1) != 0;
int offset = gprCalleeSavedRegsCount * 8 + fpSimdCalleeSavedRegsCount * _fpSimdType.GetSizeInBytes();
int offset = gprCalleeSavedRegsCount * 8 + fpSimdCalleeSavedRegsCount * _fpSimdType.ByteSize;
if (misalignedVector)
{
@@ -197,7 +197,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
mask &= ~(1u << reg2);
offset -= type.GetSizeInBytes() * 2;
offset -= type.ByteSize * 2;
if (offset != 0)
{
@@ -215,7 +215,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
}
else
{
offset -= type.GetSizeInBytes();
offset -= type.ByteSize;
if (offset != 0)
{

9
src/Ryujinx.Cpu/LightningJit/CodeGen/OperandType.cs
View File

@@ -14,14 +14,11 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen
static class OperandTypeExtensions
{
public static bool IsInteger(this OperandType type)
extension(OperandType type)
{
return type is OperandType.I32 or OperandType.I64;
}
public bool IsInteger => type is OperandType.I32 or OperandType.I64;
public static int GetSizeInBytes(this OperandType type)
{
return type switch
public int ByteSize => type switch
{
OperandType.FP32 => 4,
OperandType.FP64 => 8,

2
src/Ryujinx.Cpu/LightningJit/Translator.cs
View File

@@ -48,7 +48,7 @@ namespace Ryujinx.Cpu.LightningJit
FunctionTable.Fill = (ulong)Stubs.SlowDispatchStub;
if (memory.Type.IsHostMappedOrTracked())
if (memory.Type.IsHostMappedOrTracked)
{
NativeSignalHandler.InitializeSignalHandler();
}