JJBanana13/ryujinx
1
0
Fork 0
mirror of https://git.ryujinx.app/ryubing/ryujinx.git synced 2026-05-26 06:59:15 +00:00
Code Issues Packages Projects Releases Wiki Activity

gdb: Cleanup Debugger.cs

Browse Source 
by moving the GDB command handlers and command processor out of the class and into their own
This commit is contained in:
GreemDev
2025-10-16 17:32:04 -05:00
parent fdbdb05cb5
commit c33a97f01c
13 changed files with 1150 additions and 1075 deletions
Download Patch File Download Diff File Expand all files Collapse all files

393
src/Ryujinx.HLE/Debugger/Gdb/CommandProcessor.cs Normal file
View File

@@ -0,0 +1,393 @@
using Ryujinx.Common;
using Ryujinx.Common.Logging;
using System.Linq;
using System.Net.Sockets;
using System.Text;
namespace Ryujinx.HLE.Debugger.Gdb
{
class GdbCommandProcessor
{
public readonly GdbCommands Commands;
public GdbCommandProcessor(TcpListener listenerSocket, Socket clientSocket, NetworkStream readStream, NetworkStream writeStream, Debugger debugger)
{
Commands = new GdbCommands(listenerSocket, clientSocket, readStream, writeStream, debugger);
}
private string previousThreadListXml = "";
public void Process(string cmd)
{
StringStream ss = new(cmd);
switch (ss.ReadChar())
{
case '!':
if (!ss.IsEmpty())
{
goto unknownCommand;
}
// Enable extended mode
Commands.ReplyOK();
break;
case '?':
if (!ss.IsEmpty())
{
goto unknownCommand;
}
Commands.CommandQuery();
break;
case 'c':
Commands.CommandContinue(ss.IsEmpty() ? null : ss.ReadRemainingAsHex());
break;
case 'D':
if (!ss.IsEmpty())
{
goto unknownCommand;
}
Commands.CommandDetach();
break;
case 'g':
if (!ss.IsEmpty())
{
goto unknownCommand;
}
Commands.CommandReadRegisters();
break;
case 'G':
Commands.CommandWriteRegisters(ss);
break;
case 'H':
{
char op = ss.ReadChar();
ulong? threadId = ss.ReadRemainingAsThreadUid();
Commands.CommandSetThread(op, threadId);
break;
}
case 'k':
Logger.Notice.Print(LogClass.GdbStub, "Kill request received, detach instead");
Commands.Reply("");
Commands.CommandDetach();
break;
case 'm':
{
ulong addr = ss.ReadUntilAsHex(',');
ulong len = ss.ReadRemainingAsHex();
Commands.CommandReadMemory(addr, len);
break;
}
case 'M':
{
ulong addr = ss.ReadUntilAsHex(',');
ulong len = ss.ReadUntilAsHex(':');
Commands.CommandWriteMemory(addr, len, ss);
break;
}
case 'p':
{
ulong gdbRegId = ss.ReadRemainingAsHex();
Commands.CommandReadRegister((int)gdbRegId);
break;
}
case 'P':
{
ulong gdbRegId = ss.ReadUntilAsHex('=');
Commands.CommandWriteRegister((int)gdbRegId, ss);
break;
}
case 'q':
if (ss.ConsumeRemaining("GDBServerVersion"))
{
Commands.Reply($"name:Ryujinx;version:{ReleaseInformation.Version};");
break;
}
if (ss.ConsumeRemaining("HostInfo"))
{
if (Commands.Debugger.IsProcessAarch32)
{
Commands.Reply(
$"triple:{Helpers.ToHex("arm-unknown-linux-android")};endian:little;ptrsize:4;hostname:{Helpers.ToHex("Ryujinx")};");
}
else
{
Commands.Reply(
$"triple:{Helpers.ToHex("aarch64-unknown-linux-android")};endian:little;ptrsize:8;hostname:{Helpers.ToHex("Ryujinx")};");
}
break;
}
if (ss.ConsumeRemaining("ProcessInfo"))
{
if (Commands.Debugger.IsProcessAarch32)
{
Commands.Reply(
$"pid:1;cputype:12;cpusubtype:0;triple:{Helpers.ToHex("arm-unknown-linux-android")};ostype:unknown;vendor:none;endian:little;ptrsize:4;");
}
else
{
Commands.Reply(
$"pid:1;cputype:100000c;cpusubtype:0;triple:{Helpers.ToHex("aarch64-unknown-linux-android")};ostype:unknown;vendor:none;endian:little;ptrsize:8;");
}
break;
}
if (ss.ConsumePrefix("Supported:") || ss.ConsumeRemaining("Supported"))
{
Commands.Reply("PacketSize=10000;qXfer:features:read+;qXfer:threads:read+;vContSupported+");
break;
}
if (ss.ConsumePrefix("Rcmd,"))
{
string hexCommand = ss.ReadRemaining();
Commands.HandleQRcmdCommand(hexCommand);
break;
}
if (ss.ConsumeRemaining("fThreadInfo"))
{
Commands. Reply($"m{string.Join(",", Commands.Debugger.DebugProcess.GetThreadUids().Select(x => $"{x:x}"))}");
break;
}
if (ss.ConsumeRemaining("sThreadInfo"))
{
Commands.Reply("l");
break;
}
if (ss.ConsumePrefix("ThreadExtraInfo,"))
{
ulong? threadId = ss.ReadRemainingAsThreadUid();
if (threadId == null)
{
Commands.ReplyError();
break;
}
Commands.Reply(Helpers.ToHex(
Commands.Debugger.DebugProcess.IsThreadPaused(
Commands.Debugger.DebugProcess.GetThread(threadId.Value))
? "Paused"
: "Running"
)
);
break;
}
if (ss.ConsumePrefix("Xfer:threads:read:"))
{
ss.ReadUntil(':');
ulong offset = ss.ReadUntilAsHex(',');
ulong len = ss.ReadRemainingAsHex();
var data = "";
if (offset > 0)
{
data = previousThreadListXml;
}
else
{
previousThreadListXml = data = GetThreadListXml();
}
if (offset >= (ulong)data.Length)
{
Commands.Reply("l");
break;
}
if (len >= (ulong)data.Length - offset)
{
Commands.Reply("l" + Helpers.ToBinaryFormat(data.Substring((int)offset)));
break;
}
else
{
Commands.Reply("m" + Helpers.ToBinaryFormat(data.Substring((int)offset, (int)len)));
break;
}
}
if (ss.ConsumePrefix("Xfer:features:read:"))
{
string feature = ss.ReadUntil(':');
ulong offset = ss.ReadUntilAsHex(',');
ulong len = ss.ReadRemainingAsHex();
if (feature == "target.xml")
{
feature = Commands.Debugger.IsProcessAarch32 ? "target32.xml" : "target64.xml";
}
string data;
if (RegisterInformation.Features.TryGetValue(feature, out data))
{
if (offset >= (ulong)data.Length)
{
Commands.Reply("l");
break;
}
if (len >= (ulong)data.Length - offset)
{
Commands.Reply("l" + Helpers.ToBinaryFormat(data.Substring((int)offset)));
break;
}
else
{
Commands.Reply("m" + Helpers.ToBinaryFormat(data.Substring((int)offset, (int)len)));
break;
}
}
else
{
Commands.Reply("E00"); // Invalid annex
break;
}
}
goto unknownCommand;
case 'Q':
goto unknownCommand;
case 's':
Commands.CommandStep(ss.IsEmpty() ? null : ss.ReadRemainingAsHex());
break;
case 'T':
{
ulong? threadId = ss.ReadRemainingAsThreadUid();
Commands.CommandIsAlive(threadId);
break;
}
case 'v':
if (ss.ConsumePrefix("Cont"))
{
if (ss.ConsumeRemaining("?"))
{
Commands.Reply("vCont;c;C;s;S");
break;
}
if (ss.ConsumePrefix(";"))
{
Commands.HandleVContCommand(ss);
break;
}
goto unknownCommand;
}
if (ss.ConsumeRemaining("MustReplyEmpty"))
{
Commands.Reply("");
break;
}
goto unknownCommand;
case 'Z':
{
string type = ss.ReadUntil(',');
ulong addr = ss.ReadUntilAsHex(',');
ulong len = ss.ReadLengthAsHex(1);
string extra = ss.ReadRemaining();
if (extra.Length > 0)
{
Logger.Notice.Print(LogClass.GdbStub, $"Unsupported Z command extra data: {extra}");
Commands.ReplyError();
return;
}
switch (type)
{
case "0": // Software breakpoint
if (!Commands.Debugger.BreakpointManager.SetBreakPoint(addr, len, false))
{
Commands.ReplyError();
return;
}
Commands.ReplyOK();
return;
case "1": // Hardware breakpoint
case "2": // Write watchpoint
case "3": // Read watchpoint
case "4": // Access watchpoint
Commands.ReplyError();
return;
default:
Commands. ReplyError();
return;
}
}
case 'z':
{
string type = ss.ReadUntil(',');
ss.ConsumePrefix(",");
ulong addr = ss.ReadUntilAsHex(',');
ulong len = ss.ReadLengthAsHex(1);
string extra = ss.ReadRemaining();
if (extra.Length > 0)
{
Logger.Notice.Print(LogClass.GdbStub, $"Unsupported z command extra data: {extra}");
Commands.ReplyError();
return;
}
switch (type)
{
case "0": // Software breakpoint
if (!Commands.Debugger.BreakpointManager.ClearBreakPoint(addr, len))
{
Commands.ReplyError();
return;
}
Commands.ReplyOK();
return;
case "1": // Hardware breakpoint
case "2": // Write watchpoint
case "3": // Read watchpoint
case "4": // Access watchpoint
Commands.ReplyError();
return;
default:
Commands.ReplyError();
return;
}
}
default:
unknownCommand:
Logger.Notice.Print(LogClass.GdbStub, $"Unknown command: {cmd}");
Commands.Reply("");
break;
}
}
private string GetThreadListXml()
{
var sb = new StringBuilder();
sb.Append("<?xml version=\"1.0\"?><threads>\n");
foreach (var thread in Commands.Debugger.GetThreads())
{
string threadName = System.Security.SecurityElement.Escape(thread.GetThreadName());
sb.Append(
$"<thread id=\"{thread.ThreadUid:x}\" name=\"{threadName}\">{(Commands.Debugger.DebugProcess.IsThreadPaused(thread) ? "Paused" : "Running")}</thread>\n");
}
sb.Append("</threads>");
return sb.ToString();
}
}
}

489
src/Ryujinx.HLE/Debugger/Gdb/Commands.cs Normal file
View File

@@ -0,0 +1,489 @@
using Ryujinx.Common.Logging;
using Ryujinx.Memory;
using System;
using System.Collections.Generic;
using System.Linq;
using System.Net.Sockets;
using System.Text;
namespace Ryujinx.HLE.Debugger.Gdb
{
class GdbCommands
{
const int GdbRegisterCount64 = 68;
const int GdbRegisterCount32 = 66;
public readonly Debugger Debugger;
private readonly TcpListener _listenerSocket;
private readonly Socket _clientSocket;
private readonly NetworkStream _readStream;
private readonly NetworkStream _writeStream;
public GdbCommands(TcpListener listenerSocket, Socket clientSocket, NetworkStream readStream,
NetworkStream writeStream, Debugger debugger)
{
_listenerSocket = listenerSocket;
_clientSocket = clientSocket;
_readStream = readStream;
_writeStream = writeStream;
Debugger = debugger;
}
public void Reply(string cmd)
{
Logger.Debug?.Print(LogClass.GdbStub, $"Reply: {cmd}");
_writeStream.Write(Encoding.ASCII.GetBytes($"${cmd}#{Helpers.CalculateChecksum(cmd):x2}"));
}
public void ReplyOK() => Reply("OK");
public void ReplyError() => Reply("E01");
internal void CommandQuery()
{
// GDB is performing initial contact. Stop everything.
Debugger.DebugProcess.DebugStop();
Debugger.GThread = Debugger.CThread = Debugger.DebugProcess.GetThreadUids().First();
Reply($"T05thread:{Debugger.CThread:x};");
}
internal void CommandInterrupt()
{
// GDB is requesting an interrupt. Stop everything.
Debugger.DebugProcess.DebugStop();
if (Debugger.GThread == null || Debugger.GetThreads().All(x => x.ThreadUid != Debugger.GThread.Value))
{
Debugger.GThread = Debugger.CThread = Debugger.DebugProcess.GetThreadUids().First();
}
Reply($"T02thread:{Debugger.GThread:x};");
}
internal void CommandContinue(ulong? newPc)
{
if (newPc.HasValue)
{
if (Debugger.CThread == null)
{
ReplyError();
return;
}
Debugger.DebugProcess.GetThread(Debugger.CThread.Value).Context.DebugPc = newPc.Value;
}
Debugger.DebugProcess.DebugContinue();
}
internal void CommandDetach()
{
Debugger.BreakpointManager.ClearAll();
CommandContinue(null);
}
internal void CommandReadRegisters()
{
if (Debugger.GThread == null)
{
ReplyError();
return;
}
var ctx = Debugger.DebugProcess.GetThread(Debugger.GThread.Value).Context;
string registers = "";
if (Debugger.IsProcessAarch32)
{
for (int i = 0; i < GdbRegisterCount32; i++)
{
registers += GdbRegisters.Read32(ctx, i);
}
}
else
{
for (int i = 0; i < GdbRegisterCount64; i++)
{
registers += GdbRegisters.Read64(ctx, i);
}
}
Reply(registers);
}
internal void CommandWriteRegisters(StringStream ss)
{
if (Debugger.GThread == null)
{
ReplyError();
return;
}
var ctx = Debugger.DebugProcess.GetThread(Debugger.GThread.Value).Context;
if (Debugger.IsProcessAarch32)
{
for (int i = 0; i < GdbRegisterCount32; i++)
{
if (!GdbRegisters.Write32(ctx, i, ss))
{
ReplyError();
return;
}
}
}
else
{
for (int i = 0; i < GdbRegisterCount64; i++)
{
if (!GdbRegisters.Write64(ctx, i, ss))
{
ReplyError();
return;
}
}
}
if (ss.IsEmpty())
{
ReplyOK();
}
else
{
ReplyError();
}
}
internal void CommandSetThread(char op, ulong? threadId)
{
if (threadId is 0 or null)
{
var threads = Debugger.GetThreads();
if (threads.Length == 0)
{
ReplyError();
return;
}
threadId = threads.First().ThreadUid;
}
if (Debugger.DebugProcess.GetThread(threadId.Value) == null)
{
ReplyError();
return;
}
switch (op)
{
case 'c':
Debugger.CThread = threadId;
ReplyOK();
return;
case 'g':
Debugger.GThread = threadId;
ReplyOK();
return;
default:
ReplyError();
return;
}
}
internal void CommandReadMemory(ulong addr, ulong len)
{
try
{
var data = new byte[len];
Debugger.DebugProcess.CpuMemory.Read(addr, data);
Reply(Helpers.ToHex(data));
}
catch (InvalidMemoryRegionException)
{
// InvalidAccessHandler will show an error message, we log it again to tell user the error is from GDB (which can be ignored)
// TODO: Do not let InvalidAccessHandler show the error message
Logger.Notice.Print(LogClass.GdbStub, $"GDB failed to read memory at 0x{addr:X16}");
ReplyError();
}
}
internal void CommandWriteMemory(ulong addr, ulong len, StringStream ss)
{
try
{
var data = new byte[len];
for (ulong i = 0; i < len; i++)
{
data[i] = (byte)ss.ReadLengthAsHex(2);
}
Debugger.DebugProcess.CpuMemory.Write(addr, data);
Debugger.DebugProcess.InvalidateCacheRegion(addr, len);
ReplyOK();
}
catch (InvalidMemoryRegionException)
{
ReplyError();
}
}
internal void CommandReadRegister(int gdbRegId)
{
if (Debugger.GThread == null)
{
ReplyError();
return;
}
var ctx = Debugger.DebugProcess.GetThread(Debugger.GThread.Value).Context;
string result;
if (Debugger.IsProcessAarch32)
{
result = GdbRegisters.Read32(ctx, gdbRegId);
if (result != null)
{
Reply(result);
}
else
{
ReplyError();
}
}
else
{
result = GdbRegisters.Read64(ctx, gdbRegId);
if (result != null)
{
Reply(result);
}
else
{
ReplyError();
}
}
}
internal void CommandWriteRegister(int gdbRegId, StringStream ss)
{
if (Debugger.GThread == null)
{
ReplyError();
return;
}
var ctx = Debugger.DebugProcess.GetThread(Debugger.GThread.Value).Context;
if (Debugger.IsProcessAarch32)
{
if (GdbRegisters.Write32(ctx, gdbRegId, ss) && ss.IsEmpty())
{
ReplyOK();
}
else
{
ReplyError();
}
}
else
{
if (GdbRegisters.Write64(ctx, gdbRegId, ss) && ss.IsEmpty())
{
ReplyOK();
}
else
{
ReplyError();
}
}
}
internal void CommandStep(ulong? newPc)
{
if (Debugger.CThread == null)
{
ReplyError();
return;
}
var thread = Debugger.DebugProcess.GetThread(Debugger.CThread.Value);
if (newPc.HasValue)
{
thread.Context.DebugPc = newPc.Value;
}
if (!Debugger.DebugProcess.DebugStep(thread))
{
ReplyError();
}
else
{
Debugger.GThread = Debugger.CThread = thread.ThreadUid;
Reply($"T05thread:{thread.ThreadUid:x};");
}
}
internal void CommandIsAlive(ulong? threadId)
{
if (Debugger.GetThreads().Any(x => x.ThreadUid == threadId))
{
ReplyOK();
}
else
{
Reply("E00");
}
}
enum VContAction
{
None,
Continue,
Stop,
Step
}
record VContPendingAction(VContAction Action, ushort? Signal = null);
internal void HandleVContCommand(StringStream ss)
{
string[] rawActions = ss.ReadRemaining().Split(';', StringSplitOptions.RemoveEmptyEntries);
var threadActionMap = new Dictionary<ulong, VContPendingAction>();
foreach (var thread in Debugger.GetThreads())
{
threadActionMap[thread.ThreadUid] = new VContPendingAction(VContAction.None);
}
VContAction defaultAction = VContAction.None;
// For each inferior thread, the *leftmost* action with a matching thread-id is applied.
for (int i = rawActions.Length - 1; i >= 0; i--)
{
var rawAction = rawActions[i];
var stream = new StringStream(rawAction);
char cmd = stream.ReadChar();
VContAction action = cmd switch
{
'c' or 'C' => VContAction.Continue,
's' or 'S' => VContAction.Step,
't' => VContAction.Stop,
_ => VContAction.None
};
// Note: We don't support signals yet.
ushort? signal = null;
if (cmd is 'C' or 'S')
{
signal = (ushort)stream.ReadLengthAsHex(2);
}
ulong? threadId = null;
if (stream.ConsumePrefix(":"))
{
threadId = stream.ReadRemainingAsThreadUid();
}
if (threadId.HasValue)
{
if (threadActionMap.ContainsKey(threadId.Value))
{
threadActionMap[threadId.Value] = new VContPendingAction(action, signal);
}
}
else
{
foreach (var row in threadActionMap.ToList())
{
threadActionMap[row.Key] = new VContPendingAction(action, signal);
}
if (action == VContAction.Continue)
{
defaultAction = action;
}
else
{
Logger.Warning?.Print(LogClass.GdbStub,
$"Received vCont command with unsupported default action: {rawAction}");
}
}
}
bool hasError = false;
foreach (var (threadUid, action) in threadActionMap)
{
if (action.Action == VContAction.Step)
{
var thread = Debugger.DebugProcess.GetThread(threadUid);
if (!Debugger.DebugProcess.DebugStep(thread))
{
hasError = true;
}
}
}
// If we receive "vCont;c", just continue the process.
// If we receive something like "vCont;c:2e;c:2f" (IDA Pro will send commands like this), continue these threads.
// For "vCont;s:2f;c", `DebugProcess.DebugStep()` will continue and suspend other threads if needed, so we don't do anything here.
if (threadActionMap.Values.All(a => a.Action == VContAction.Continue))
{
Debugger.DebugProcess.DebugContinue();
}
else if (defaultAction == VContAction.None)
{
foreach (var (threadUid, action) in threadActionMap)
{
if (action.Action == VContAction.Continue)
{
Debugger.DebugProcess.DebugContinue(Debugger.DebugProcess.GetThread(threadUid));
}
}
}
if (hasError)
{
ReplyError();
}
else
{
ReplyOK();
}
foreach (var (threadUid, action) in threadActionMap)
{
if (action.Action == VContAction.Step)
{
Debugger.GThread = Debugger.CThread = threadUid;
Reply($"T05thread:{threadUid:x};");
}
}
}
internal void HandleQRcmdCommand(string hexCommand)
{
try
{
string command = Helpers.FromHex(hexCommand);
Logger.Debug?.Print(LogClass.GdbStub, $"Received Rcmd: {command}");
string response = command.Trim().ToLowerInvariant() switch
{
"help" => "backtrace\nbt\nregisters\nreg\nget info\nminidump\n",
"get info" => Debugger.GetProcessInfo(),
"backtrace" or "bt" => Debugger.GetStackTrace(),
"registers" or "reg" => Debugger.GetRegisters(),
"minidump" => Debugger.GetMinidump(),
_ => $"Unknown command: {command}\n"
};
Reply(Helpers.ToHex(response));
}
catch (Exception e)
{
Logger.Error?.Print(LogClass.GdbStub, $"Error processing Rcmd: {e.Message}");
ReplyError();
}
}
}
}

160
src/Ryujinx.HLE/Debugger/Gdb/Registers.cs Normal file
View File

@@ -0,0 +1,160 @@
using ARMeilleure.State;
using Ryujinx.Cpu;
using System;
namespace Ryujinx.HLE.Debugger.Gdb
{
static class GdbRegisters
{
/*
FPCR = FPSR & ~FpcrMask
All of FPCR's bits are reserved in FPCR and vice versa,
see ARM's documentation.
*/
private const uint FpcrMask = 0xfc1fffff;
public static string Read64(IExecutionContext state, int gdbRegId)
{
switch (gdbRegId)
{
case >= 0 and <= 31:
return Helpers.ToHex(BitConverter.GetBytes(state.GetX(gdbRegId)));
case 32:
return Helpers.ToHex(BitConverter.GetBytes(state.DebugPc));
case 33:
return Helpers.ToHex(BitConverter.GetBytes(state.Pstate));
case >= 34 and <= 65:
return Helpers.ToHex(state.GetV(gdbRegId - 34).ToArray());
case 66:
return Helpers.ToHex(BitConverter.GetBytes((uint)state.Fpsr));
case 67:
return Helpers.ToHex(BitConverter.GetBytes((uint)state.Fpcr));
default:
return null;
}
}
public static bool Write64(IExecutionContext state, int gdbRegId, StringStream ss)
{
switch (gdbRegId)
{
case >= 0 and <= 31:
{
ulong value = ss.ReadLengthAsLEHex(16);
state.SetX(gdbRegId, value);
return true;
}
case 32:
{
ulong value = ss.ReadLengthAsLEHex(16);
state.DebugPc = value;
return true;
}
case 33:
{
ulong value = ss.ReadLengthAsLEHex(8);
state.Pstate = (uint)value;
return true;
}
case >= 34 and <= 65:
{
ulong value0 = ss.ReadLengthAsLEHex(16);
ulong value1 = ss.ReadLengthAsLEHex(16);
state.SetV(gdbRegId - 34, new V128(value0, value1));
return true;
}
case 66:
{
ulong value = ss.ReadLengthAsLEHex(8);
state.Fpsr = (uint)value;
return true;
}
case 67:
{
ulong value = ss.ReadLengthAsLEHex(8);
state.Fpcr = (uint)value;
return true;
}
default:
return false;
}
}
public static string Read32(IExecutionContext state, int gdbRegId)
{
switch (gdbRegId)
{
case >= 0 and <= 14:
return Helpers.ToHex(BitConverter.GetBytes((uint)state.GetX(gdbRegId)));
case 15:
return Helpers.ToHex(BitConverter.GetBytes((uint)state.DebugPc));
case 16:
return Helpers.ToHex(BitConverter.GetBytes((uint)state.Pstate));
case >= 17 and <= 32:
return Helpers.ToHex(state.GetV(gdbRegId - 17).ToArray());
case >= 33 and <= 64:
int reg = (gdbRegId - 33);
int n = reg / 2;
int shift = reg % 2;
ulong value = state.GetV(n).Extract<ulong>(shift);
return Helpers.ToHex(BitConverter.GetBytes(value));
case 65:
uint fpscr = (uint)state.Fpsr | (uint)state.Fpcr;
return Helpers.ToHex(BitConverter.GetBytes(fpscr));
default:
return null;
}
}
public static bool Write32(IExecutionContext state, int gdbRegId, StringStream ss)
{
switch (gdbRegId)
{
case >= 0 and <= 14:
{
ulong value = ss.ReadLengthAsLEHex(8);
state.SetX(gdbRegId, value);
return true;
}
case 15:
{
ulong value = ss.ReadLengthAsLEHex(8);
state.DebugPc = value;
return true;
}
case 16:
{
ulong value = ss.ReadLengthAsLEHex(8);
state.Pstate = (uint)value;
return true;
}
case >= 17 and <= 32:
{
ulong value0 = ss.ReadLengthAsLEHex(16);
ulong value1 = ss.ReadLengthAsLEHex(16);
state.SetV(gdbRegId - 17, new V128(value0, value1));
return true;
}
case >= 33 and <= 64:
{
ulong value = ss.ReadLengthAsLEHex(16);
int regId = (gdbRegId - 33);
int regNum = regId / 2;
int shift = regId % 2;
V128 reg = state.GetV(regNum);
reg.Insert(shift, value);
return true;
}
case 65:
{
ulong value = ss.ReadLengthAsLEHex(8);
state.Fpsr = (uint)value & FpcrMask;
state.Fpcr = (uint)value & ~FpcrMask;
return true;
}
default:
return false;
}
}
}
}

93
src/Ryujinx.HLE/Debugger/Gdb/Xml/aarch64-core.xml Normal file
View File

@@ -0,0 +1,93 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2009-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.aarch64.core">
<reg name="x0" bitsize="64"/>
<reg name="x1" bitsize="64"/>
<reg name="x2" bitsize="64"/>
<reg name="x3" bitsize="64"/>
<reg name="x4" bitsize="64"/>
<reg name="x5" bitsize="64"/>
<reg name="x6" bitsize="64"/>
<reg name="x7" bitsize="64"/>
<reg name="x8" bitsize="64"/>
<reg name="x9" bitsize="64"/>
<reg name="x10" bitsize="64"/>
<reg name="x11" bitsize="64"/>
<reg name="x12" bitsize="64"/>
<reg name="x13" bitsize="64"/>
<reg name="x14" bitsize="64"/>
<reg name="x15" bitsize="64"/>
<reg name="x16" bitsize="64"/>
<reg name="x17" bitsize="64"/>
<reg name="x18" bitsize="64"/>
<reg name="x19" bitsize="64"/>
<reg name="x20" bitsize="64"/>
<reg name="x21" bitsize="64"/>
<reg name="x22" bitsize="64"/>
<reg name="x23" bitsize="64"/>
<reg name="x24" bitsize="64"/>
<reg name="x25" bitsize="64"/>
<reg name="x26" bitsize="64"/>
<reg name="x27" bitsize="64"/>
<reg name="x28" bitsize="64"/>
<reg name="x29" bitsize="64"/>
<reg name="x30" bitsize="64"/>
<reg name="sp" bitsize="64" type="data_ptr"/>
<reg name="pc" bitsize="64" type="code_ptr"/>
<flags id="cpsr_flags" size="4">
<!-- Stack Pointer. -->
<field name="SP" start="0" end="0"/>
<!-- Exception Level. -->
<field name="EL" start="2" end="3"/>
<!-- Execution state. -->
<field name="nRW" start="4" end="4"/>
<!-- FIQ interrupt mask. -->
<field name="F" start="6" end="6"/>
<!-- IRQ interrupt mask. -->
<field name="I" start="7" end="7"/>
<!-- SError interrupt mask. -->
<field name="A" start="8" end="8"/>
<!-- Debug exception mask. -->
<field name="D" start="9" end="9"/>
<!-- ARMv8.5-A: Branch Target Identification BTYPE. -->
<field name="BTYPE" start="10" end="11"/>
<!-- ARMv8.0-A: Speculative Store Bypass. -->
<field name="SSBS" start="12" end="12"/>
<!-- Illegal Execution state. -->
<field name="IL" start="20" end="20"/>
<!-- Software Step. -->
<field name="SS" start="21" end="21"/>
<!-- ARMv8.1-A: Privileged Access Never. -->
<field name="PAN" start="22" end="22"/>
<!-- ARMv8.2-A: User Access Override. -->
<field name="UAO" start="23" end="23"/>
<!-- ARMv8.4-A: Data Independent Timing. -->
<field name="DIT" start="24" end="24"/>
<!-- ARMv8.5-A: Tag Check Override. -->
<field name="TCO" start="25" end="25"/>
<!-- Overflow Condition flag. -->
<field name="V" start="28" end="28"/>
<!-- Carry Condition flag. -->
<field name="C" start="29" end="29"/>
<!-- Zero Condition flag. -->
<field name="Z" start="30" end="30"/>
<!-- Negative Condition flag. -->
<field name="N" start="31" end="31"/>
</flags>
<reg name="cpsr" bitsize="32" type="cpsr_flags"/>
</feature>

159
src/Ryujinx.HLE/Debugger/Gdb/Xml/aarch64-fpu.xml Normal file
View File

@@ -0,0 +1,159 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2009-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.aarch64.fpu">
<vector id="v2d" type="ieee_double" count="2"/>
<vector id="v2u" type="uint64" count="2"/>
<vector id="v2i" type="int64" count="2"/>
<vector id="v4f" type="ieee_single" count="4"/>
<vector id="v4u" type="uint32" count="4"/>
<vector id="v4i" type="int32" count="4"/>
<vector id="v8f" type="ieee_half" count="8"/>
<vector id="v8u" type="uint16" count="8"/>
<vector id="v8i" type="int16" count="8"/>
<vector id="v8bf16" type="bfloat16" count="8"/>
<vector id="v16u" type="uint8" count="16"/>
<vector id="v16i" type="int8" count="16"/>
<vector id="v1u" type="uint128" count="1"/>
<vector id="v1i" type="int128" count="1"/>
<union id="vnd">
<field name="f" type="v2d"/>
<field name="u" type="v2u"/>
<field name="s" type="v2i"/>
</union>
<union id="vns">
<field name="f" type="v4f"/>
<field name="u" type="v4u"/>
<field name="s" type="v4i"/>
</union>
<union id="vnh">
<field name="bf" type="v8bf16"/>
<field name="f" type="v8f"/>
<field name="u" type="v8u"/>
<field name="s" type="v8i"/>
</union>
<union id="vnb">
<field name="u" type="v16u"/>
<field name="s" type="v16i"/>
</union>
<union id="vnq">
<field name="u" type="v1u"/>
<field name="s" type="v1i"/>
</union>
<union id="aarch64v">
<field name="d" type="vnd"/>
<field name="s" type="vns"/>
<field name="h" type="vnh"/>
<field name="b" type="vnb"/>
<field name="q" type="vnq"/>
</union>
<reg name="v0" bitsize="128" type="aarch64v" regnum="34"/>
<reg name="v1" bitsize="128" type="aarch64v" />
<reg name="v2" bitsize="128" type="aarch64v" />
<reg name="v3" bitsize="128" type="aarch64v" />
<reg name="v4" bitsize="128" type="aarch64v" />
<reg name="v5" bitsize="128" type="aarch64v" />
<reg name="v6" bitsize="128" type="aarch64v" />
<reg name="v7" bitsize="128" type="aarch64v" />
<reg name="v8" bitsize="128" type="aarch64v" />
<reg name="v9" bitsize="128" type="aarch64v" />
<reg name="v10" bitsize="128" type="aarch64v"/>
<reg name="v11" bitsize="128" type="aarch64v"/>
<reg name="v12" bitsize="128" type="aarch64v"/>
<reg name="v13" bitsize="128" type="aarch64v"/>
<reg name="v14" bitsize="128" type="aarch64v"/>
<reg name="v15" bitsize="128" type="aarch64v"/>
<reg name="v16" bitsize="128" type="aarch64v"/>
<reg name="v17" bitsize="128" type="aarch64v"/>
<reg name="v18" bitsize="128" type="aarch64v"/>
<reg name="v19" bitsize="128" type="aarch64v"/>
<reg name="v20" bitsize="128" type="aarch64v"/>
<reg name="v21" bitsize="128" type="aarch64v"/>
<reg name="v22" bitsize="128" type="aarch64v"/>
<reg name="v23" bitsize="128" type="aarch64v"/>
<reg name="v24" bitsize="128" type="aarch64v"/>
<reg name="v25" bitsize="128" type="aarch64v"/>
<reg name="v26" bitsize="128" type="aarch64v"/>
<reg name="v27" bitsize="128" type="aarch64v"/>
<reg name="v28" bitsize="128" type="aarch64v"/>
<reg name="v29" bitsize="128" type="aarch64v"/>
<reg name="v30" bitsize="128" type="aarch64v"/>
<reg name="v31" bitsize="128" type="aarch64v"/>
<flags id="fpsr_flags" size="4">
<!-- Invalid Operation cumulative floating-point exception bit. -->
<field name="IOC" start="0" end="0"/>
<!-- Divide by Zero cumulative floating-point exception bit. -->
<field name="DZC" start="1" end="1"/>
<!-- Overflow cumulative floating-point exception bit. -->
<field name="OFC" start="2" end="2"/>
<!-- Underflow cumulative floating-point exception bit. -->
<field name="UFC" start="3" end="3"/>
<!-- Inexact cumulative floating-point exception bit.. -->
<field name="IXC" start="4" end="4"/>
<!-- Input Denormal cumulative floating-point exception bit. -->
<field name="IDC" start="7" end="7"/>
<!-- Cumulative saturation bit, Advanced SIMD only. -->
<field name="QC" start="27" end="27"/>
<!-- When AArch32 is supported at any Exception level and AArch32
floating-point is implemented: Overflow condition flag for AArch32
floating-point comparison operations. -->
<field name="V" start="28" end="28"/>
<!-- When AArch32 is supported at any Exception level and AArch32
floating-point is implemented:
Carry condition flag for AArch32 floating-point comparison operations.
-->
<field name="C" start="29" end="29"/>
<!-- When AArch32 is supported at any Exception level and AArch32
floating-point is implemented:
Zero condition flag for AArch32 floating-point comparison operations.
-->
<field name="Z" start="30" end="30"/>
<!-- When AArch32 is supported at any Exception level and AArch32
floating-point is implemented:
Negative condition flag for AArch32 floating-point comparison
operations. -->
<field name="N" start="31" end="31"/>
</flags>
<reg name="fpsr" bitsize="32" type="fpsr_flags"/>
<flags id="fpcr_flags" size="4">
<!-- Flush Inputs to Zero (part of Armv8.7). -->
<field name="FIZ" start="0" end="0"/>
<!-- Alternate Handling (part of Armv8.7). -->
<field name="AH" start="1" end="1"/>
<!-- Controls how the output elements other than the lowest element of the
vector are determined for Advanced SIMD scalar instructions (part of
Armv8.7). -->
<field name="NEP" start="2" end="2"/>
<!-- Invalid Operation floating-point exception trap enable. -->
<field name="IOE" start="8" end="8"/>
<!-- Divide by Zero floating-point exception trap enable. -->
<field name="DZE" start="9" end="9"/>
<!-- Overflow floating-point exception trap enable. -->
<field name="OFE" start="10" end="10"/>
<!-- Underflow floating-point exception trap enable. -->
<field name="UFE" start="11" end="11"/>
<!-- Inexact floating-point exception trap enable. -->
<field name="IXE" start="12" end="12"/>
<!-- Input Denormal floating-point exception trap enable. -->
<field name="IDE" start="15" end="15"/>
<!-- Flush-to-zero mode control bit on half-precision data-processing
instructions. -->
<field name="FZ16" start="19" end="19"/>
<!-- Rounding Mode control field. -->
<field name="RMode" start="22" end="23"/>
<!-- Flush-to-zero mode control bit. -->
<field name="FZ" start="24" end="24"/>
<!-- Default NaN mode control bit. -->
<field name="DN" start="25" end="25"/>
<!-- Alternative half-precision control bit. -->
<field name="AHP" start="26" end="26"/>
</flags>
<reg name="fpcr" bitsize="32" type="fpcr_flags"/>
</feature>

27
src/Ryujinx.HLE/Debugger/Gdb/Xml/arm-core.xml Normal file
View File

@@ -0,0 +1,27 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2008 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.arm.core">
<reg name="r0" bitsize="32"/>
<reg name="r1" bitsize="32"/>
<reg name="r2" bitsize="32"/>
<reg name="r3" bitsize="32"/>
<reg name="r4" bitsize="32"/>
<reg name="r5" bitsize="32"/>
<reg name="r6" bitsize="32"/>
<reg name="r7" bitsize="32"/>
<reg name="r8" bitsize="32"/>
<reg name="r9" bitsize="32"/>
<reg name="r10" bitsize="32"/>
<reg name="r11" bitsize="32"/>
<reg name="r12" bitsize="32"/>
<reg name="sp" bitsize="32" type="data_ptr"/>
<reg name="lr" bitsize="32"/>
<reg name="pc" bitsize="32" type="code_ptr"/>
<reg name="cpsr" bitsize="32" />
</feature>

86
src/Ryujinx.HLE/Debugger/Gdb/Xml/arm-neon.xml Normal file
View File

@@ -0,0 +1,86 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2008 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.arm.vfp">
<vector id="neon_uint8x8" type="uint8" count="8"/>
<vector id="neon_uint16x4" type="uint16" count="4"/>
<vector id="neon_uint32x2" type="uint32" count="2"/>
<vector id="neon_float32x2" type="ieee_single" count="2"/>
<union id="neon_d">
<field name="u8" type="neon_uint8x8"/>
<field name="u16" type="neon_uint16x4"/>
<field name="u32" type="neon_uint32x2"/>
<field name="u64" type="uint64"/>
<field name="f32" type="neon_float32x2"/>
<field name="f64" type="ieee_double"/>
</union>
<vector id="neon_uint8x16" type="uint8" count="16"/>
<vector id="neon_uint16x8" type="uint16" count="8"/>
<vector id="neon_uint32x4" type="uint32" count="4"/>
<vector id="neon_uint64x2" type="uint64" count="2"/>
<vector id="neon_float32x4" type="ieee_single" count="4"/>
<vector id="neon_float64x2" type="ieee_double" count="2"/>
<union id="neon_q">
<field name="u8" type="neon_uint8x16"/>
<field name="u16" type="neon_uint16x8"/>
<field name="u32" type="neon_uint32x4"/>
<field name="u64" type="neon_uint64x2"/>
<field name="f32" type="neon_float32x4"/>
<field name="f64" type="neon_float64x2"/>
</union>
<reg name="d0" bitsize="64" type="neon_d"/>
<reg name="d1" bitsize="64" type="neon_d"/>
<reg name="d2" bitsize="64" type="neon_d"/>
<reg name="d3" bitsize="64" type="neon_d"/>
<reg name="d4" bitsize="64" type="neon_d"/>
<reg name="d5" bitsize="64" type="neon_d"/>
<reg name="d6" bitsize="64" type="neon_d"/>
<reg name="d7" bitsize="64" type="neon_d"/>
<reg name="d8" bitsize="64" type="neon_d"/>
<reg name="d9" bitsize="64" type="neon_d"/>
<reg name="d10" bitsize="64" type="neon_d"/>
<reg name="d11" bitsize="64" type="neon_d"/>
<reg name="d12" bitsize="64" type="neon_d"/>
<reg name="d13" bitsize="64" type="neon_d"/>
<reg name="d14" bitsize="64" type="neon_d"/>
<reg name="d15" bitsize="64" type="neon_d"/>
<reg name="d16" bitsize="64" type="neon_d"/>
<reg name="d17" bitsize="64" type="neon_d"/>
<reg name="d18" bitsize="64" type="neon_d"/>
<reg name="d19" bitsize="64" type="neon_d"/>
<reg name="d20" bitsize="64" type="neon_d"/>
<reg name="d21" bitsize="64" type="neon_d"/>
<reg name="d22" bitsize="64" type="neon_d"/>
<reg name="d23" bitsize="64" type="neon_d"/>
<reg name="d24" bitsize="64" type="neon_d"/>
<reg name="d25" bitsize="64" type="neon_d"/>
<reg name="d26" bitsize="64" type="neon_d"/>
<reg name="d27" bitsize="64" type="neon_d"/>
<reg name="d28" bitsize="64" type="neon_d"/>
<reg name="d29" bitsize="64" type="neon_d"/>
<reg name="d30" bitsize="64" type="neon_d"/>
<reg name="d31" bitsize="64" type="neon_d"/>
<reg name="q0" bitsize="128" type="neon_q"/>
<reg name="q1" bitsize="128" type="neon_q"/>
<reg name="q2" bitsize="128" type="neon_q"/>
<reg name="q3" bitsize="128" type="neon_q"/>
<reg name="q4" bitsize="128" type="neon_q"/>
<reg name="q5" bitsize="128" type="neon_q"/>
<reg name="q6" bitsize="128" type="neon_q"/>
<reg name="q7" bitsize="128" type="neon_q"/>
<reg name="q8" bitsize="128" type="neon_q"/>
<reg name="q9" bitsize="128" type="neon_q"/>
<reg name="q10" bitsize="128" type="neon_q"/>
<reg name="q11" bitsize="128" type="neon_q"/>
<reg name="q12" bitsize="128" type="neon_q"/>
<reg name="q13" bitsize="128" type="neon_q"/>
<reg name="q14" bitsize="128" type="neon_q"/>
<reg name="q15" bitsize="128" type="neon_q"/>
<reg name="fpscr" bitsize="32" type="int" group="float"/>
</feature>

14
src/Ryujinx.HLE/Debugger/Gdb/Xml/target32.xml Normal file
View File

@@ -0,0 +1,14 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2009-2013 Free Software Foundation, Inc.
Contributed by ARM Ltd.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
<!DOCTYPE target SYSTEM "gdb-target.dtd">
<target>
<architecture>arm</architecture>
<xi:include href="arm-core.xml"/>
<xi:include href="arm-neon.xml"/>
</target>

14
src/Ryujinx.HLE/Debugger/Gdb/Xml/target64.xml Normal file
View File

@@ -0,0 +1,14 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2009-2013 Free Software Foundation, Inc.
Contributed by ARM Ltd.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
<!DOCTYPE target SYSTEM "gdb-target.dtd">
<target>
<architecture>aarch64</architecture>
<xi:include href="aarch64-core.xml"/>
<xi:include href="aarch64-fpu.xml"/>
</target>